DataGeneral NOVA in Verilog

Note: You need knowledge of both Verilog and the NOVA architecture to find this even remotely useful.


Currently Missing/ TODOs

I'm debating whether I just use a standard soft-core processor with some glue logic to interface to the NOVA PIO bus. This would allow me to implement all devices in software which has the advantage of it being easier to feed data into it.


Every character corresponds to a cycle, a cycle takes one clock tick.
F=Fetch, E=Execute, I=Indirect Traverse, M=Memory, O=I/O Writeback

FSM Clock Cycles
Compute Instruction FFE 3
Memory Direct FFEM 4
Memory Indirect FFEI[...]E 5+n
Input Output FFE[...]O 4+n

Memory access is pipelined to reduce the amount of cycles needed, for example the DSZ/ISZ instructions go through the following steps (on direct memory): The ALU is completely implemented in combinatoric logic. This will decrease the possible clock speed (depending on FPGA) but shouldn't matter in this case, since the whole thing will be able to run way faster than the original anyways.

CPU States

Examining the nova_cpu.v file you will see that the main CPU is implemented using a state machine with the following states:

IO States

The file nova_io.v contains a state-machine that handles IO bus operations, it has the following states:

How to Simulate

Adjust the line containing $readmemh in nova_ram.v to point to a hexfile (see below) you want to load. Furthermore you may have to adjust the program counter r_PC in nova_cpu.v to point to the correct entry point.

You can generate Hexdecimal number dumps required for the verilog simulation under UNIX systems with:
xxd -c2 -ps somefile.bin > somefile.hex

Programmable I/O Bus (PIO)

The PIO bus is roughly based upon the Wishbone bus. It contains the following Signals, all of which latch on a positive clock edge and are HIGH active. From the point of view of the slave device they are sampled on a positive edge clock when bs_stb is asserted. S->M signals must be in a high impedance state when undriven. See nova_io_dummy.v for an example.
bs_rst M->S
bs_stb M->S
bs_we M->S
bs_adr<0:7> M->S
bs_dout<0:15> M->S
bs_din<0:15> S->M
bs_ack S->M

The address path bs_adr is mapped as follows:


This project is not associated or endorsed by Data General, any company who maintains the properties of Data General or any ex-employee of Data General.
By Jan Adelsbach (Contact/Impressum) see also my other HDL CPU Projects.